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The furthest STI Etch i want to point two things, one is the aspect ratio of this
etch, so we etch into the silicon using nitrite as the hard mark.
So if you look at this STI feature, it's it has the
silicon, and then we have the nitrite and the hard mask.
And aspect ratio, which are involved
in this etch are are typically off more than they can be off more than 10 is to 1.
That is the height of the edge can be more than 10 times the width.
So this S this shallow in this shallow trench isolation is
really a misnomer because quite deep if you look at the aspect ratio.
And the other thing is the chemistry, so this we
use dry or plasma based chemistry to to, for this STI.
And the typical chemistry used for silicon
edge, if you use a chlorine based chemistry.
So you'll, silicon reacts with this chlorine ion then
it find the SiClx, which is essentially a volatile compound,
and it goes away.
It goes away from this trench, and that's why
you're able to continue to etch and make this feature.
So the next thing you do after you have made
this STI feature is now you need to etch it.
Sorry, you need to fill it, so the next step is to fill this
trench with an oxide. So, again the
main challenge now again is that you have a very high aspect ratio feature to fill.
So you have this trench with an aspect ratio of more than 10 is to 1.
So, we use either you know, a plasma base or, or
a very high density plasma to fill up this shallow trench isolation.
And then the next step after that is the chemin
is the CMP steps, the ones you have filled up, your STI,
that fill or flow then you get this kind of a profile.
And then you want to level everything back, so you
want to level everything back into into a flat surface.
So the step that is used for that
is chemical-mechanical polishing, and it's it's depicted over here.
And so this this cartoon over here shows the CMP equipment, and
it's essentially the same equipment that you use for any, any kind of polishing.
So it involves this table, rotating table which is made up of an abrasive material.
And then you you mount your wafer to this carrier, and then
you spin this carrier again and you apply a downward force.
And then you keep on flowing this Slurry so it, it, the surface is
[INAUDIBLE],
with the Slurry. And then you keep on rotating this wafer,
and depending upon how much downward pressure you apply you
polish your surface. Shown here is a picture showing one of the
CMP tools. So we can identify this table over here.
And we can see this wafer wafer carrier.
And the wafer is probably attached below this carrier.
And this there'll be also Slurry on the surface.
So the surface would be wet with the slurry.
The chemistry of the slurry is also very important
depending upon what material we are trying to polish.
We'll use a different slurry.
But it in principle, it looks like any other any other polishing tool.
Like a tool that you'll use to polish your knives.
it, it looks, the operating principle's the same.
And it's it's a very unique tool.
if you go in a fab, this is probably the tool which
would be you know, making most of this squeaky kind of noise.
And it produces a very signature defect pattern as well.
So if you, if you have
if you have a wafer and you get a
particle, you get a particle over here in the RCMP.
So if you, the defect part in the producer because everything is rotating over here.
So you have this table rotating and you have your wafer rotating, so you,
that defect also produces like the rotating key, key, key kind of a pattern.
So it's it was polis, technology was pio,
pioneered really by IBM in, you know, the last decade.
And now it's being it's used very pervasively in the industry.
So what you get after you do their CMP, after you
do your chemical mechanical polishing, you get a very flat surface.
And so you you, you get this flat surface with with your with your
silicon, and then you have this oxide fill in this trench.
So, so shown here is a, is a, is a, is a, TM image showing this
So we started with this
[UNKNOWN],
and we etched this STI feature into our, into our,
into our silicon, then we filled it up with oxide and then you do a CMP.
So you're, you have now again back this
flat surface and your oxide is filling this feature.
So now that we are done with STI, the next the
next the next step in the process show is to form these well implants.
So these well implants, they're defined essentially, are active regions.
So you, these.
By active region is mean is that the
devi, the regions where the devices would be made.
So you define where will you make your p channel device and
you make, you define where you'll make your n, n channel device.
So, what you do is essentially, you again pattern
your resist, and you will just exposed the
region where you want to say make p channel devices.
So these are these are p moss devices or they have essentially a n type substrate.
So then you implant implat this region with say
arsenic or phosphorous. And if you create this end well.
And then you do, then you use another layer for this, and you
expose the region where you want to maybe make your, make your n-MOS devices.
So you want to make your n-channel devices over here, so you need a p-type substrate.
So you implant this
with boron, and once you are done implanting, you do an activation
[UNKNOWN]
to activate these dopants. The next set of process steps
involve the formation of the gate stack. So, the first
thing that we need to form to make a gate is is the gate
insulator, or the the gate dielectric. And
the the way it's done is that you you
oxidize your silicon, so it's a thermally grown oxide.
And you grow this silicon oxide on the active area,
on, on the area of where your silicon is exposed.
And then you color it out with a poly, so you do a blanket deposition of
poly-silicon. And you cover this whole wafer with
the poly-silicon.
And the next step is to pattern this poly-silicon into the gate lights.
So we cover it up with a hard mass, so you have this poly, then you put a hard mass.
Then you put photo resist, then you pattern that photo resist
to form these gate lines, and to form this, gate pattern.
And then you
etch that gate pattern into your poly-silicon.
So you etch your poly material to form these set of gate lines.
So now you have these gate lines these are gate lines let's say to p
types of devices, and then these are gate lines which are connecting
to n channel devices. And if you, if you come and
take an aerial picture of your, your of your chip, it would
look, something, like this. So remember, I'd had shown this picture to
describe the estram cell, where I had shown you the different transistors.
It was taken at this prime,this point of time
in your process flow where you have to define your
gate stocks, so you can where you are identifying
your gate lines, so you can see these gate lines.
Some of these gate lines would be
running on let's say p-channel transistors, and the
rest of them you know, the next few would be running on say, n-channel transistors.
And now you can see that your you can probably start
our undefined transistors at this point of time.
So remember earlier we identified these two transistors, one being
n type and one being p type, whose gates are connected.
So they form an inverter.
And this was connected to this other inverter which was formed
by these set of transistors. Again one being p type another
being n type.
And they are, they were essentially cross connected so you can now see your skeleton
of your SRAM cell taking into shape over here.