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Hello my name is Axel Scherer.
I will give you a quick introduction into UVM for SystemVerilog.
This is the first in a series of short videos that cover the basic concept.
The target audience are both designers and and verification engineers that deal with
IPs, System on a Chip and System development.
So why do we need UVM? We have been use Verilog for over 20 years now to model
hardware devices and to some degree to test them. But as complexities of these devices
have increase, so has the verification effort. And Verilog is just not good anymore to verify
these complex systems. So one path to solve this problem was the
introduction of SystemVerilog. Now, SystemVerilog is not just an incremental
increase over Verilog. It is a significant addition, right. And it
is much much more than just a few language extensions.
SystemVerilog adds a lot of dimensions to the language.
Now, let's start with legacy HDL, Verilog. That's a great thing. You start with something
that you are familiar with.
And it's of course fully intentional. So you have a good footing.
But the first step of the addition is object oriented programming.
So you model your verification environment in a dynamic way. You allocate objects and
all that kind of stuff.
So this is very orthogonal to your modeling of your hardware device.
That alone is a big deal.
On top of that you add specific concepts related to verification, such as constrained random
test generation. And once you introduce randomization you need
something to measure it, such as coverage and things like that.
So these are just a few of the aspects of SystemVerilog. There is a lot more.
The problem now is with all this space, all these dimensions - how you're gonna build
your verification environment?
If you just do your own thing, you're probably gonna end up in chaos.
And that's exactly what UVM is trying to address. It performs a standardization. A standardization
of how to build your environment, right. To master all this power, right. How to build
your testbench. How to generate test. How to collect coverage. How to introduce
your scoreboards and all that stuff. Let's do it in the same way - in a standard
way.
And the way this standardization evolved is basically by incorporating all of the best
practices that have been developed in advanced verification over the last 10 years and
more. One of the primarily concepts is reuse, which
is essential for complex verification environments.
Now, talk is cheap, right. We can do videos like this, write a lot of papers, books, you
know, guides and all that good stuff. But that's not gonna
be enough. Human nature - we will stray from recommendation.
So the cool thing about UVM is that all of this wisdoms is absorbed in a class library
built in SystemVerilog. So here you have a higher level of abstraction, your components
can be derived from base classes and things like this.
So a lot of the IP from the best practices is embedded in the UVM class library.
And just by using that, you are already way ahead, right.
You have a lot of pre-verified components. You have much more functionality
than basic SystemVerilog, that's just not in the language per se.
And all of this is really customized to improve your verification productivity.
Now if you follow this class library in the UVM recommendations you really have
a powerful environment. And you join the large ecosystem of the growing user
base of this methodology.
On top of this it is, of course, not just a standard. It's an open standard and
it's vendor independent.
So UVM in a nutshell is basically containing all these different degrees of freedom
you have with a massive language like SystemVerilog and distilling it down to
a standard way of using it - to building a verification environment.
Right, this way you can interoperate between your teams, between your staff
and the whole electronics ecosystem.
In the next couple of videos we will dive into details of the subcomponents and
build it up. We show you code and give you some demos.
You can find these videos either on this YouTube channel or at
suppor.cadence.com at the video library for the Incisive Simulator.
Have a great day and talk to you soon.