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Hi. Welcome to SystemVue. We’re going to discover the Fast Circuit Envelope Models
for RFIC verification. The products you’ll be seeing are the SystemVue Platform 1461
and the W1719 RF System Design Kit. Our objective in this demo is to verify the LTE performance
of an RFIC transceiver. In this case, it’s a low noise amp in seconds instead of hours.
So let’s get started.
The first thing we need to do is place the model in SystemVue. I’m going to go to the
part selector, put in fast, place the fast circuit envelope model and we’ll double
click on it. Notice it has no ports or pins. I browse to the file and select this file.
When I instantiate it, the internal nodes and input/output ports have been selected.
If there are internal nodes in the model file, I can select them. I can see their frequencies
of operation. I can also look at the amplitude range and other characteristics of this particular
file. This model has been extracted for three millivolts to 300 millivolts which is about
-50 dBm to -10 dBm at a frequency of 2.6 GHz. When I do that, you can see that I have the
correct number of input and output ports, and I finish wiring it into my circuit.
Now before we continue, you might ask, “What does this represent?” So let’s take a
moment to understand what exactly a fast circuit envelope model is. First we start with a transistor
level physical design using Agilent GoldenGate within an Enterprise RFIC design flow. You
have two methods. One is to directly connect to SystemVue and wrap a system around that
RFIC component and test it against LTE, baseband algorithms or even compare it with waveforms
from test equipment. That direct co-sim requires active connection of both environments. An
alternative is to export a fast circuit envelope model file which is then imported into SystemVue
and run about 1,000 to 100,000 times faster than the native RFIC would have run with full
parasitics and all the envelope level details.
What we will do is verify the integrity of this model file, exactly what’s in it, and
then apply this technique to a real LTE example and show you how you can use the VSA software
and facilities within SystemVue to actually verify that in a very rapid way.
Back in SystemVue if I simulate this, you can see that I have a voltage ramp. That voltage
ramp is modulated and that becomes effectively a power sweep. If I look at the gain and phase
versus power, I can see that I have about two degrees of AM to PM and as I ramp the
input voltage level, the output voltage level clips. If I plot that on a log scale, I can
see from a power perspective that as I ramp the input power, the output power does compress
and clip at some point. So I have some amount of confidence in the basic methodology of
this simulation, and we’re ready to go to the next step.
Okay. This example is just a little bit more sophisticated. We have an LTE, uplink coded
source that is up converted and passed through a CMOS power amp. The CMOS power amp is a
2 ½ GHz and we are measuring the spectrum, the CCDF and the AM to AM and AM to PM. So
let’s take it all the way to the maximum and you’ll see the LTE simulation completes
in about three seconds. This is about 150,000 points so it’s about 50,000 points per second.
You can easily see we’re into compression. The CCDF shows what we’re almost clipping
and there’s quite a bit of spectral regrowth.
If I change and tune this power level, you can see that the analysis updates fairly quickly.
So with this you can explore a lot of different cases very quickly to investigate the robustness
of this particular analog design. So in this LTE workspace, we’re accounting for power
dependence and frequency dependence of the device. What we’re not necessarily seeing
as easily is the non-linear memory effects. If that particular device -- this is a power
amp -- but if it had a whole transceiver with an up or down conversion stage, we would account
for frequency translation, multiple input and output ports including control pins, as
well as internal nodes.
In fact, these fast circuit envelope models can be extracted at various input and output
complex loads, various bias states, process corners, temperatures, control states and
voltages and with models for all of these things, you can successfully investigate these
effects directly from SystemVue.
Now coming back to our circuit, let’s go back to our model and find a different model
that has memory effects. Let me show you the effect of memory effects. Here in a few seconds
we have changed the model and now see the non-deterministic nature of path dependents
to the signal where self-heating and other effects are causing this particular model
to have behavioral phenomena that really are harder to predict with static, non-linear
models. In fact, it kind of points out that these models are easy to export and there’s
no hand coding involved when exporting them from GoldenGate and on the SystemVue side,
you can use them with drag and drop simplicity. The system architect really doesn’t have
to drag around the whole RFIC environment. He can do these things extremely quickly and
with great confidence and the accuracy of the result.
There’s one last thing I want to show and that’s using the VSA software to demodulate
this particular simulation result. The 89600 VSA is a different piece of software than
SystemVue. It’s actually an instrument frontend and what we’re going to do is have both
the VSA and SystemVue available at the same time and when I change the power level on
SystemVue, you can watch the simulation update and see the dynamic behavior in other change
in the VSA. Watch the EVM change. This is error vector magnitude versus subcarrier of
the LTE signal and we’re seeing a very high EVM. You watch that settle back down. You
can see the spectral regrowth and there’s a number of measurements I can make on the
VSA side. For example, I can show occupied bandwidth which is about 4 ½ MHz and I can
show integrated band power with these markers and that is showing -14 dBm. If I come over
here to the side, you can see that I can quickly assess adjacent channel linkage ratio as well
as EVM and all these other factors. So in a matter of seconds, I’ve requalified my
PA for its LTE performance.
So in conclusion, what we’ve seen is the fast circuit envelope model provides a great
deal of convenience and speed. That speed allows you to test against real standards
and specifications. They come directly from the IC design flow without a lot of human
intervention. The separation of the file from the original Enterprise IC environment minimizes
the license use and makes those transportable which makes the system architect controls
his own destiny and does it with confidence and with that speed, he can look at a greater
proportion of the test plan for LTE as well as de-risk a tape out for a significant CMOS
mask.
That concludes the demo of the Fast Circuit Envelope Model. For more videos on SystemVue,
go to www.agilent.com/find/eesof-systemvue-videos. Thanks very much and good luck in your next
design.