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The waveforms on the oscilloscope screen are measured from a PLL circuit.
This is the circuit constructed on board.
This circuit contains a CD4046 and some other components.
A square wave logic signal is generated from a signal generator and injected into CD4046.
The PLL process generates another logic signal...
which has same frequency and same phase angle and is locked with input signal.
Input signal (green one) & Output signal (blue one).
Lock range frequency of the PLL circuit is selected between 35Hz and 65Hz.
Input and output signals stay locked between these limit frequencies.
Frequency of the signals can be read at the bottom right of the screen. It is 38Hz now.
Now, the input signal frequency will be increased from the signal generator and...
the PLL action will be seen from the oscilloscope screen.
The input frequency of the PLL is increasing now.
Yes, the process is seen clearly.
Input frequency of the PLL increased to 48Hz...
and firstly, the output signal (blue one) lost the lock position.
Then, the phase comparator inside the IC generated an error between two signals.
Finally, the closed loop controller compansated the error signal and locked the signals again.
Some changes on the input frequency...
Input frequency is 55Hz now.
Let's try the maximum frequency.
60Hz...
A little change, 61Hz...
Now, the IC is nearly operating at its maximum limit condition.
A little increase again, 62Hz...
As you see the settling time is also increased, because the controller is at limit condition.
And now, a little increase at the input frequency makes the system unstable,...
because the frequency is out of the lock range.
As you see, the signals are not locked anymore.
Why does this happen? A voltage controlled oscillator (VCO) is working inside the IC.
These two resistors set the minimum and maximum operating frequencies of the VCO.
At design process, these frequencies were selected as 35Hz and 65Hz respectively.
Now the input frequency is out of VCO's frequency band, therefore the system is unstable.
Input frequency is decreased again. A fast decrease.
Out of range again, we are at below the minimum frequency, it is 28Hz now.
Now it is 70Hz and not locked. A decrease to 48Hz makes the system stable.
Increase... 59Hz and locked.
Decrease... This was a little more decrease.
And this is the minimum limit condition. Controller tries to lock the signals. Nearly zero voltage is applied to the control pin of the VCO.
A little increase in frequency makes the PLL stable and locked again.
This PLL circuit operates as frequency multiplier.
For frequency multiplying process some logic components are used.
These tree ICs are logic components, they are decade (10) counters.
At this circuit only two of them are operating.
Since these "10" counters are cascaded, total counting number is "100".
Now, i will measure the high frequency (100 times input frequency) signal which is locked to the input signal.
On the screen, you can see a high frequency signal with input signal. Let's change the time division of the oscilloscope...
Yes, it is seen that the VCO output signal (whose frequency is 100 times input signal) is locked with input signal (green one).
Effects of input frequency changes can be seen also.
Thanks for listening!
Res. Asst. Furkan Baskurt - ITU Power Electronics Laboratory
www.powerelectronics.itu.edu.tr