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seeing about the flip flop against the latch the latch is store a bit o and 1 and flip
flop also do that but a flip flop as a extra additional control called the clock when the
clock is high then data can be stored in flip flop and when the clock is low output rented
even when change in the input we saw the basic SR flip flop and D flip flop where a single
bit data can be stored with a single input data input by connecting sr through an invert-er
then we talked about the condition of 1 1 being not permitted for SR flip flop see other
can do some thing about it we modify the input and gate into a three input NAND gate and
found that it is possible to have an operation correspondence the S=1 and R=1 where in the
flip flop output keeps changing constantly 0 to 1 1 to 0 so for as long as clock is high
when clock is low of course it retains its content.now the very frequent change in the
output with an SR flip flop s=1 r=1 in put the NAND gate disturbing because the we dot
want that type of behavior it called racing racing is in not inter served behavior on
the other hand it is nice idea to have a input condition 1 1 where the output changes for
present state to complimentary state.