Tip:
Highlight text to annotate it
X
The next module then this front end of the line process flow is
the formation of a junction. So the next thing we need to do is form
our source and drain junction, and that typically involves implanting the species.
So we want to implant dopants, and then we want to
activate those dopants to form this so then rain, junctions.
So this implants it consist of
multiple, multiple species that are implanted and each of
them has a different purpose. So typically, in any
advanced, transistor, or any short channel, transistor.
You have, three main implants. So the first one is,
a halo implant.
So this is an implant which is of the same species as we are a substrate.
So suppose you have a n type substrate.
So this is a n plus implant, that, if you do.
Implant of the same species, and you do it at
a side angle such that you essentially implant this region.
And then the next implant is the source and rain extension
implant, so this is the source and rain extension implant and this is
a relatively lower-doping implant, again, and it's
off a different species. So this one would be a p implant.
And then the final implant is your, sole drain, deep sole
drain implant, so your final implant is as deep soldiering implant.
And again
it's of the opposite species as the substrate
and it's if of even higher drop rate.
So this would be a p plus.
So let's say you had an n type substrate of the arsenic.
So this halo implant would be, we hide those low energy arsenic implant.
And then your then your source drain extension would be a boron implant.
And then your source drain would be another boron implant
with a much higher dose and a slightly higher energy.
So the purpose of these halo and these source drain
extensions, for the purpose of this halo implant and this.
Soul drain extension implant is to essentially minimize
your short channel effects, and we will discuss
how these help in minimizing the short channel effects in a later video, but
right now just assume that to minimize these short channel effects we need this.
Halo implant, and we need this soldering extension implant.
So how do we enable these different, how do we enable these different implants?
So the way it's actually done is that you
first start with the wafer that you obtain after your gate patterning.
So after your gate patterning you had.
Something like this, so you have your polygate which was pattern.
And then you do your source drain extension implants.
This would be in this case would be a boron
implant And then you do your halo implant and this
halo implant is done at an angle so it it penetrates through it penetrates
through your, through your gate and goes inside here on this, this arrow region.
And so, it's done at an angle, and
you rotate your wafer while you're doing this implant.
So this, your wafer would be inclined at this angle, and
you'll be implanting your Species from the top at the same
time you will keep on rotating this wafer so you get
implants species from here and you can also get implant species
from here and that helps you form this HALO, HALO, HALO region.
And once you have done your soldering extension
implant, and you have done your halo implant,
you actually, cover you form a spacer, so you found this nitrite spacer,
and then you implant your, deeper, and, high energy, or
high dose, I know the soldering implant. So, once you have found
the spacer, then, you can safely implant boron again.
And that would go, that would be for much higher dose and that could
be of slightly higher energy, and then you get this, source drain implant.
So, let, let me show you in, this in, 3D.
So let's say you had, you had your, you had these
bevel and well regions, so you cover one of them, so you cover your bevel regions.
And then you do your soldering extension implant.
So, you implant this boron sensor
so, you implant boron to form your soldering extension,
and then you implant your arsenic at an angle.
So, this arsenic is implanted at an angle, let's say
a 30 degree angle and that's from the halo region.
So, this form this halo region over here.
And then you, cover, so right now we implanted the n-well.
Now we'll cover the
n-well, so we cover the n-well with this,
photoresist and, we implant our p-well, and again.
First we want to form the soldering extension so we
can either implant arsenic or we can implant phosphorus, and then
we want to form a halo for this so we
implant boron at an angle, we implant boron at an angle.
And again it forms these sorts and this, it forms
these halo regions, as shown here, and then the next step you do is form a
spacer, so the way we form a spacer is you deposit a conformer film of nitride.
So you deposit this, it's a silicon nitride film.
Then form a leaf throughout your wafer so it covers the entire wafer.
And then you do a RIE edge or you do a dry edge.
So you remove
the nitride on, on the flat surface. What you give
nitride in the side wall so you from the side was spacer of nitride.
Once we have deposited this side wall spacer, the next step
is to do is these deep, source and rain implants, so again we
cover one type of transistors with photoresist to recover
the p with photoresist.
And in the end, where we implanted uh,with boron and then
we strip off the photo-resist and then you essentially cover with photo-resist again.
And then expose your other transistors. And in this case, you then
implanted with the arsenic so now you have formed your, your implanted your
slow drain regions and you have finished all the implants.
And the next step is to essentially anneal the implants, and,
the next step you want to do is do a high-temperature step.
That will activate these door pins and these anneal requirements
are driven by actually the device requirements shown here as the ITRS
road Map. And what it dictates is that you control
the sharp channel effects in your device. You are and your scaling your uh,gate
[UNKNOWN]
your gate outside thickness so you want to scale your junction depth so
let's say that Junction depth should keep on reducing every year.
At the same time it says that you want lower resistance also because you don't
want your transistor performance to be limited
by your, resistance from your source and drain.
So you want to keep your
source and drain resistance at a constant in order to use it.
So it says that you want to reduce your source and
drain extension at the same time, you want to make it shallower.
So these are opposing requirements, so you want to make
a region with the with a very shallow depth.
At the same time you want it to have lower resistivity.
So the only way you can achieve this is you want higher and
higher doping concentration so you want
higher and higher concentration of your dopant.
At the same time you want them to be very shallow.
So you want your junction net to be very shallow.
So this, this requires, you know, your
Anneals to be done at much higher temperature.
And you want them to be done at much shorter time.
So if you look at
the landscape of anneals that have been used in the semiconductor processing.
So this is shown over here.
They have been going up in temperature and they have been going down in time.
So starting with the furnace anneal where you will essentially just
to lower up these wafers into a furnace and you'll let them
[UNKNOWN]
for hours.
Then the next evolution of anneal that you do this thing called RTA anneal
then followed by this this, followed by spike anneal.
And then you now do millisecond on these.
And going forward people are even talking about doing microsecond on these.
And nanosecond on these.
At the same time you, you start *** above temperatures
from 700 to 800, all the way to, you know.
Right now reaching the melting point of silicon.
So this is depicted in this chart over here
[INAUDIBLE]
which shows how your, how your how your anneal
time has been going from you know hours all the way in the furnace anneal.
To a RTP Anneal where are a Spike Anneal
where there used to be in seconds and going
to Flash Anneal with the other ten milliseconds and
all the way going to Laser Anneal which has time
scale of microseconds.
And so its a,its a, its a exactly
quite a complicated problem having where these temperature in
a way short time and how to cool it off in a millisecond time frame of event.
we will discuss this in, in a later video, but I just want to mention that this is
how the Anneal roadmap has been evolving that you go in lower in time and
higher in temperature.
Note the Anneal step was where we encountered
the highest temperature or the highest thermal budgets in the process flow.
So we, we saw that, you know, we use
near or above 1000°C to to activate the implants.
And then once you have activated our implants we
are done forming our junctions.
The next the next step is to form
contacts to these Contacts to the source drain implants.
So we imply a process which is called self align silicide so we need to form a
contact or a silicide with our silicon and the process which is implied is a,
is a self aligned process to form the silicide.
Silicide also know as Salicide so the way this works is you have formed your
junctions now and you also have the
spacer materials separating your gate and your soldiering.
And what you do is essentially you do a blank in
deposition of nickel so you deposit blanket layer of nickel everywhere.
So you have this nickel conformly
covering your whole wafer. And then what you do is do a anneal step.
This is a low temperature anneal.
In the Anneal temperature of around 300 to 400
degree centigrade and what happened at that temperature id your nickle
reacts with your silicon and it forms this It's nickel monosilicide
base which is a non-resistivity base.
An important point is that again thermal budgets are important
over here so you don't want to go to a higher temperature.
So if you go to a temperature which are high
it forms this nickel di-silicide which has a higher in this
[UNKNOWN]
so we want to make sure that the temperature
and the step is, stays between, 300 to 400
range.
And at this temperature, what happens is your nickel reacts with your silicon to
form this nickel silicide, so this nickel silicide is shown over here.
In this dashed region, so this is where your nickel was exposed to
silicon, or polysilicon, and it formed this nickel silicide over here.
on the side wall,
this nickel does not react with the nitride, so on the side wall,
it remains in this nickel because it does not react with this nitrate.
So what you do next is, so you prepared to do wet etch, and you remove your
unreactored, nickel from the side wall, so this nickel is removed.
And you're left with, your nickel, your reactored
nickel which from this nickel silici.
So you essentially now have your nickel sillicide on top of your gate.
You also have it on top of your, source. On top of, your drain.
[INAUDIBLE].
So, using this, using this space.
We are, able to obtain this, self alignment
between, The spacer, the spacer helped
in, forming these nickel silicide on
the source and drain and the gate without them shorting each other So that's why
it's called a self-aligned process flow, because
of this spacer, which helps in forming
all the silicide on the source and
drain together, and the gate, without shorting them.
So the spacer not only helps in the in the implants where you want to form
that soldering extension but it also helps in this in this uh,silicide formation.
And once
we have we have formed this silicide we essentially we are done with
forming our transistors so we now want to protect them and keep them safe.
So we cover them with a layer of nitride followed
by a layer of oxide and this is a conformal
depositions so it it preserves the topography of our transistor
and the, next you might want to polish them for further processing
so you do the CMP step.
And now you have the nice transistor, nice
little transistor and their covered with this oxide layer.
And that
lower of front end of the line process flow, and now you know you can kick the
bucket down to the back end of the line
to finish the rest of your micro processor flow.