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Hello, everyone.
Today we will introduce a new element, CMOS.
It's derived from MOSFET.
Here C
means complementary.
What's the complementary things
and its advantage?
Firstly, let's analyze
the power loss of logic gates formed by MOSFET.
Take inverter as an example.
When Ugs is one,
MOSFET is turned on
and acts as a resistor
seen from drain and source terminals.
This is the circuit model.
There's a current path
and the power loss of logic gate contains
the power loss of RL and Ron.
We assume a typical value
So the power loss of the logic gate is calculated out to be 0.25mW.
Don't underestimate this value.
For a single logic gate,
it's a tiny power loss.
But there're hundreds of millions
of transistors in CPU.
We assume there're about 40 million transistors in a CPU
and all of them are made up of N-enhanced MOSFET 29 00:01:36,476 --> 00:01:38,161 and all of them formed into inverters,
then the power loss 31 00:01:40,354 --> 00:01:44,222 of CPU is about 10000W.
It's really a huge value.
You all have the experience of using a computer
and it's obviously unacceptable and the actual situation can't be like this.
So how to decrease the power loss of logic gate?
From the equivelant circuit, you can find
one of the improvements
is to debase the voltage of power supply.
In fact, this is also the measure taken in electronic industry.
CPU's power supply voltage is from original 5V
to 3V later and to less than 2V today.
The aim is to decrease CPU power loss.
However there's a limit to this decrease.
The low power supply voltage
has impact on the reliability of CPU.
So it's not a fundamental measure.
Can we suppose
if there's no current path
when MOSFET is turned on,
then power loss is zero?
In other words, can we improve the logic gates structure
to ensure there's no current path
when MOSFET is turned on?
Thus the power loss is completely eliminated.
This is the original intention of CMOS.
Our previous analysis
is based on N-enhanced MOSFET.
This is its circuit symbol.
When Ugs is greater than Uds plus Ut
i.e.Uds is less than Ugs minus Ut,
MOSFET is turned on and acts as a resistor.
Corresponding to N-enhanced MOSFET,
there's a P-enhanced MOSFET.
This is its circuit symbol.
Pay attention to the difference between circuit symbols
of N-enhanced MOSFET and P-enhanced MOSFET,
the direction of this arrow.
The operation mechanisms
of N-enhanced MOSFET and P-enhanced MOSFET are basically similar.
The difference is
when P-enhanced MOSFET is connected to external power source,
the source terminal is not connected to the negative electrode of power source
but to the positive electrode of power source.
So its turn-on condition
is Usg is greater than Usd plus Ut.
With these condition MOSFET is turned on 77 00:04:19,822 --> 00:04:22,604 and acts as a resistor between its drain and source terminals.
For distinguish,
the resistance is represented as RonP
and this is represented as RonN.
Connect the drain terminals
of P-enhanced MOSFET and N-enhanced MOSFET together,
Connect their gate terminals,
and apply the same control signal. A new element
called CMOS is formed.
Complementary is derived from
the complementary structure of
P-enhanced MOSFET and N-enhanced MOSFET.
Let's see the function
of CMOS connected to
logic signals.
The source of PMOS is connected to high level i.e.logic one,
and the source of NMOS is connected to low level i.e.logic zero.
Now input a logic signal.
If the input signal
is logic one,
for PMOS,
Usg equals to zero
since its source terminal now is connected to logic one too.
While for NMOS,
Ugs equals to logic one.
THerefore for the PMOS above,
it's turned off because Usg is zero,
while for the NMOS below,
it's turned on because Ugs is one,
The conduction resistance is RonN.
Since
there's no current path,
Uout equals to logic zero.
The output is zero when the input is one.
Next consider the case that
the input is zero.
For the PMOS above,
Usg equals to logic one
since its source terminal is connected to logic one now.
For the NMOS below,
Ugs equals to logic zero
since its source terminal is connected to the ground.
Therefore the PMOS is turned on
since Usg is one and its conduction resistance is RonP.
NMOS below is turned off.
We can see
there's no current path,
so Uout is connected to high level i.e.Uout equals to one.
Let's look at the two logic relations.
When input is one, output is zero.
When input is zero, output is one.
This is right the logic of inverter
and in fact this is an inverter formed by CMOS.
Compared with the previous inverter formed only by NMOS,
there's
no current path inside logic gate
no matter what input signal is.
So inverter formed by CMOS has no power loss
in steady state.
It is really very exciting.
Now please think about such a question.
The complementary structure of CMOS we discussed just now
is PMOS above and NMOS below.
Can their position
be interchanged?
In other words, can we realize the logic of inverter correctly
aftering interchanging their positions?