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This is a working demonstration of the EE3 Lab Project 1 Experiment.
The logic is set to the "recording" mode. Changing the analog voltage from 0v through 5v will cause the 7-Segment to change it's display.
We are now saving the 1st digit: "0". Notice we are using the manual burst & trigger options, in order to guarantee that only one memory cell will be written to.
Saving the 2nd digit: "5".
Saving the 3rd digit: "1".
And the 4th digit: "2".
And the 5th digit: 12 (in BCD), which gives us "u".
The 6th: "3".
The 7th: "5".
The 8th: "9".
And the last digit to be recorded: "3".
We have finished recording. The logic is set to the reading mode, and the RAM and counter clock trigger is set to "internal".
The recorded digits are displayed in a cyclic order: "0512u3593". This is, btw, the EE3 Lab course ID.
Changing the analog voltage input during reading mode will not cause any change: The A/D is actually not enabled and thus will not interfere with the bus.
The digits "0512u3593" are displayed in a cyclic order as long as the logic stays in the reading mode.
Good Luck!