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Öa lot of built-in amplifier test benches that I donít have to reconfigure. I can just
go ahead and open up one of these templates. The amplifier, the 3-section amplifier is
in that big symbol in the middle with the three triangles on it. And I was able to run
a series of simulations, looking at different power sweeps, different gains, what the transient
waveform would look like, gain flatness.
And this is pretty much class A, class A/B type of analysis. If I was so inclined to
be looking for something more along the lines of just power gain, where Iím more interested
in load-pull contours, those templates have been predefined for me. I can easily bring
in load-pull contours, see what my device is doing, see where Iíd want to match for
be it gain power or deficiency or power itself. A lot of these test benches have been set
up for you.
As well as being able to look at more complicated sweeps where, in this case, Iím varying my
bias voltages, and Iím looking at power contours and power added efficiency to get some idea
of what would happen if I ñ does the battery droop to those bias voltages changed over
the course of use of the amplifier.
So depending on what style of design Iím using or what Iím particularly looking at,
there are several different setups within the ADS environment for amplifier design already
sitting there for you to use. So once the design was starting to look, eh, fairly reasonable
from my standpoint, I wanted to go ahead and generate a layout, which I did. I moved this
into our layout environment. I synchronized it from the schematic, generated my layout
here to get an idea of what this would look like.
At these frequencies, I just used very simple biasing techniques where I have a compacitor
to ground giving me a good short point, and then my line, the lower green lines to the
blue lines on the north and the south, bring my bias in over a quarter wave. So now Iím
using that, having a short at the capacitor point or at the via and rotating that to the
main line to be an open.
And for me, this has traditionally been very, very effective for biasing. And we didnít
have any oscillations, weíll see later, in the measurement, so this seems to work pretty
well, once again. But this was just step one of getting the layout. What weíre going to
see next is in cleaning it up a little bit, changing things around within the TQP13 PDK,
weíve implemented a personality tool bar, if you will, for MMIC here. And there are
a lot of specialized techniques here for selecting, deselecting layout elements like transmission
lines, converting them to different layers, inserting vias, chopping, changing things
around. So I was able to quickly route over the poly on the input of the device and send
the via down to a lower-level metal and route and connect up my compacitor and my resistor.
At this point, I could have run a mail DRC, which is a DRC that Iím running on a TriQuint
server in Oregon. And Iím going to take the necessary layout, send it to that server,
have it checked on the TriQuint server, and then the results are going to be sent back
to me. Thatís implemented directly on this toolbar. So I could have done it that way
or with the advent of ADS 2009, weíve built our own integrated desktop DRC.
TriQuint is currently into the ñ working with Agilent. Weíre currently implementing
the rules for these. And once we have that, weíll be able to, as weíve done here, just
point to a particular design rule deck when the DRC engine is run locally and get our
results. Make any corrections we need to. And then once we have the corrections for
our DRC, we would be able to invoke our desktop LVS engine where weíre now looking back between
the layout itself and verifying that we still meet the schematic representation of that
that we havenít, in somehow alternating or changing the layout for DRC completeness or
cleanness, that we havenít modified our connectivity.
So with the Update 1 of 2009 ADS will have a complete front-to-back flow within the environment,
able to find design differences, complete the DRC and get a clean ready-to-build layout,
which is what weíre seeing here now.
So now we put it together with the launches, as you can see, so we can probe it on a prober
station later on. Weíve done that. We can also, within the ADS environment, easily visualize
what this looks like from the third dimension to be able to look at how the vias are pushing
through the dielectric or just to see it from a different angle, other than the standard
2D view looking down at it.
From this we generated a reticle cell for the fabrication process. As you can see, we
put a few additional elements on there. We put the input and middle stage by itself and
the middle and output stage by themselves. We put some individual devices, as well as
some calibration and matching structures that weíre going to be needing later on when we
go into test. And so a little bit of a close-up of what that feedback ended up looking like.
This was kind of what we were looking for to really stabilize that device, if you remember,
and it came out very similar to what we were first kind of looking at in the first routing.
Adjusted the links a little bit was really about all we did. So with the design being
clean from the DRC standpoint, LVS associated it back with the schematic. We knew we were
ready to build. And we went ahead and went into the fab.
And as you can see, we have the fabricated parts here. We have a three-stage amplifier
in the TQP13 process. Weíve fabricated those, as well as some our standards here. So these
are individual devices, one with and without feedback, so we can check those individually.
And weíve built some calibration standards ëcause weíre going to ñ want to double
check, even if weíre not using these as our cal standards, I like to be able to check
ñ we have a via there for checking how our shorts acting, an open, we have a resistor,
and we have a through line in there as well from the cal standards we ended up coming
up with.
We then mounted this on a metal test board thatís gold flashed. We used conductive epoxy
and parallel plate-type capacitors that we bonded to. So on the north and the south ñ
on the north weíre going to have our drainage voltage, which is about four volts from the
south where we have our gate on the south, which ended up optimally being about 0.7,
0.8 volts. Then on the left is our input, on the right is our output. So once we were
fixtured up, we were ready to go into the lab.
And we have a very nice Cascade Elite 300 prober that we have here with four probe heads
on it. You can also see the PNA kind of hiding and buried in the middle of that in the background
of the prober. So weíre using an Agilent PNA, obviously, to do our measurements. And
here weíre lining up on a particular device. We tried ñ we have a couple different variations
of the amplifier itself, but actually the one we designed was sort of our nominal case
that we designed for 100 micron substrate thickness that worked the best, reinforcing
the specs of the process.
So weíre lining up on the device here, and then weíre connecting it up with the probes
and getting ready for test. So this was the test environment that weíre testing under.
And looking at our measurement results thus far, we have several more things to measure
and more to be done.
We can see that we actually measured ñ we were low on frequency. We were expecting around
60, weíre actually working more around 52 GHz, but we are keeping a fair amount of power
considering weíre not well matched in that range. Only about 6 or 7 dB return loss in
that range was encouraging. So weíre losing some power to mismatch loss, but we did end
up being pretty low in frequency.
Again, because of the time constraints, we had not had a chance to do a lot of additional
modeling around it, but one of the first things we want to look at is well, we didnít pay
attention to the actual layout from an EM standpoint. What might some critical areas
be? Well, certainly we have that long stub, which could move us off a little bit in frequency,
but probably more likely weíre going to have an awful lot of coupling right in the ñ where
the device is mounted because of the close proximity to the lines.
The way we have to air bridge into the device itself we canít have a good solid line coming
up, so you can see the air bridge is coming into the device. So letís go ahead. And just,
to this point, weíve looked mainly at just the first stage. So what has this ñ weíve
run an EM simulation on this to get an idea of what this looks like from a 3D EM standpoint.
Even though Method of Moments is a planer technique, we have extended the algorithm
to understand metal thicknesses and couplings between metal, so we do understand vertical
and horizontal side walls with ñ on the planar structures. And, again, this is completely
integrated within our layout environment. We didnít go somewhere else. We just were
able to take out the device and section out the piece of metal that we wanted to look
at. We ran the simulation on it, used Method of Moments.
And then we took those results, the layout look alike element here just so we can see
where weíre connecting up. We took that back into the schematic environment and weíre
comparing it to our first stage of the amplifier that we actually built. And when we did this,
weíre able to see that that did, in fact, shift the frequency. And it shifted it just
exactly to where weíre seeing it right now.
So we need to do the other stages, which will ñ I think weíll be sending out some sort
of amendment to this ñ addendum to this talk so that you can see that doing EM on the entire
amplifier, as I expect, should move it down to the 50 GHz range, get us the right gain
back out, but also give us a position to where now we know where the amplifierís working
at. Again, this is an ongoing project for us to test out a flow, so weíre going to
scale this up. I would think would be the first thing, just scaling from the standpoint
of frequency, and then adjusting slightly if need be to get our gain back.
But this proves out or reinforces that knowing up front we really should have done some EM
simulation, but often, we know we have ñ weíre constrained by time. So given that
we use the empirical models for the transmission lines, they really didnít turn out too bad,
I donít think, considering weíre looking at 60 GHz as our tune frequency, and we have
52. So in addition to looking at the performance of the amplifier itself, we also wanted to
look at it under the conditions here theoretically or with simulation look at it under the WPAN
Agilent has a product called SystemVue that integrates or is linked to ADS. And here weíre
developing wireless library standards. So we have a WPAN, as well as other these high
definition type signal standards implemented within the ADS environment. We have sources.
We have test benches. We have the receiver. So we can set up a detailed signal that can
be used even in ADS simulation or can actually be taken out to hardware and also used with
Agilent test equipment.